An input output (TO) circuit enables transmission of signals in/out of an integrated circuit (IC). A programmable IO supports multiple standards, e.g., high voltage standards, low voltage standards, high speed standards, low speed standards and etc. The programmable IO is commonly available in Programmable Logic Device (PLD).
The programmable IO is typically built with 2.5V Complementary Metal Oxide Semiconductor (CMOS) transistors. The 2.5V CMOS transistor has an acceptable reliability profile to support high voltage standards, but at the same time, has a performance bottleneck when supporting low voltage standards. The electrical current propagating through the drain of a 2.5V transistor is significantly insufficient for the purpose of IO functions for the low voltage standards. There are techniques for overcoming low drain current in 2.5V transistors, by way of increasing planar width on the 2.5V transistors, but such techniques may increases the total capacitance within the transistor.
The programmable IO supports high speed memory interface standards, which require relatively fast transistors in terms of switching on and off within the programmable IO. However, one of the drawbacks of relatively fast transistors is having a low overdrive voltage limit. Hence, when utilizing fast transistors, the programmable IO may not support high voltage standards, e.g., standards that utilize voltages of 2.5V or 3.3V.
It is within this context that the embodiments described herein arise.